1. Field
The present innovations relate generally to high-speed synchronous SRAM and RLDRAM applications, and, more specifically, to systems and methods having power up aspects such as adaptive power up features.
2. Description of Related Information
Output buffer initialization techniques are commonly used to prevent leaked current during random power up sequences for high-speed synchronous SRAM and RLDRAM applications. Furthermore, various kinds of output buffer initialization schemes are implemented in attempt to achieve better performance and/or high speed operation.
In general, existing output buffers 100 (or “DQ” buffers), such as shown in FIG. 1, provide output buffer initialization in a typical memory circuit in order to read out Memory Core 105 data of Peripheral Circuit(s) 105 after completing power up sequences. Here, given two or more power supply voltages (e.g., VDD, VDDQ) associated with such output buffer circuitry, the power up sequence may often occur in an undesired sequence, even though a specified order may be shown in a relevant data sheet. For example, in existing circuitry, a second power supply voltage VDDQ may be powered up before a first power supply voltage VDD. FIGS. 2 and 3 illustrate such a circuit 200 (e.g., powered by VDD and VDDQ) and an illustrative timing diagram with internal signals PUB, PD, PU, PDB and output DQi, showing aspects of certain power up sequences occurring out of order, such as may occur at initialization. As seen in FIG. 3, as a result of power up of VDDQ prior to VDD, internal signals (e.g. PU) may be brought into undesired states (here, high) and/or VDDQ may otherwise be leaked-through, such that the output DQi also achieves an undesired state (again, high here in FIG. 3, i.e., until VDD is then powered on).
As set forth below, one or more aspects of the present inventions may overcome these or other drawbacks and/or otherwise impart innovative features.